Today I would like to highlight the talk of S. Wildermann on "Symbolic Design Space Exploration for Multi-Mode Reconfigurable Systems" (F. Reimann, D. Ziener and J. Teich are co-authors.) In their paper the authors address the question how to choose optimal profiles and layouts for FPGAs (Field Programmable Gate Arrays) that are partially reconfigurable during run-time. A growing number of embedded systems has to support different operation modes with different task and load profiles depending on their current requirement. FPGAs that can be partially reconfigured during run-time are a very interesting, emerging technology and usually the basic idea is to have a processor core and I/O interfaces statically configured into the FPGA and to load special accelerators into the reconfigurable area as needed. Thus, the required chip size is limited (which reduces the production costs) and unused accelerators do not add to the power consumption. However, each reconfiguration consumes time and power requiring a careful trade-off. Furthermore, a multitude of other problems are still open, starting from architectural efficiency (see e.g. our paper at CHES 2011, "An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension") over the question addressed in this talk - how to satisfy the constraints and requirements while avoiding more reconfiguration than needed - to security questions such as the verification and authentication of configuration streams and isolation of security relevant modules.
The common hardware platform made this talk interesting to me - I'm not going to pretend to be an expert for automated Design Space Exploration and the associated optimization algorithms but let me try to explain one interesting point made in the talk: The authors found that existing DSE approaches cannot trivially be adopted to the scenario of reconfigurable devices as the reconfiguration cost adds a new dimension to the problem: What used to be a static problem (production cost) has now run-time cost added to it. They use a SAT solver to efficiently explore design spaces in lower dimensions so that the SAT solver can focus on what it does best: solving scalar and linear equations. Additionally they use an evolutionary algorithm to choose optimal values for the missing dimensions. (This combined use of an evolutionary algorithm and a SAT solver has been introduced as "SAT decoding" by Lukasiewycz et al. ) Wildermann et al. develop a model for reconfigurable design spaces and use the SAT decoding on two case studies to efficiently find optimized solutions that fullfil the constraints. As follow up work, I'd like to see how security constraints can be added to the new model of reconfigurable design spaces.