Embedded Systems Week day 3

CODES+ISSS (one of the three ESWeek main conferences) offered a very interesting session on emerging new techniques for non-volatile memories. The talks of this session gave a nice survey of recent advances in the quest to replace current DRAM as well as SRAM caches with new, denser (and bigger) memories based on technologies such as Phase Change Memory (PCMs) and Spin-Transfer Torque RAM (STT-RAM). For some reason unbeknownst to me, the announced fourth talk on Memristors was replaced by a talk on the future of Flash memory and 3D stacking of flash memory.

Phase Change Memory cells consist of a GST (Ge2Sb2Te5) chalcogenide block which can be either in its amorphous phase (0, high resistance) or in its crystalline phase (1, lower resistance). The GST is placed between Vdd (heater) and GND. In his talk Youtao Zhang showed that the first PCM based products have been announced and highlighted some of the advantages and challenges for PCM to replace/enhance current DRAMs. One of the issues is quite obvious: Writing a bit, i.e. changing the state of one GST block requires a lot of energy and time. Another issue is less obvious but maybe even more problematic: While DRAM basically works forever, PCM will fail after roughly 100 million writes with process variations adding a relatively large amount of uncertainty. The third issue is related to security: usage of non-volatile memory as DRAM replacement makes cold-boot attacks a lot easier. On the plus side, the non-volatility of PCM would enable instant-on functionality and PCM is competitive with RAM for reading speed, reading energy and idle power leakage and thus out-performing NAND-Flash. Youtao Zhang then explained some of the techniques used to mitigate the draw backs, which fall into one of the following categories:

• Reducing the number of writes
• Wear-levelling
• Salvaging

My impression was that PCM may be a good technology to replace NAND-Flash in solid state disks but that it will be difficult to replace DRAM entirely with PCM. Splitting the RAM into a DRAM and a PCM part, as outlined by Youtao Zhang, may be a more realistic solution.

Spin-Transfer Torque Memory consists of a Magnetic Junction Tunnel which (in its simplest version) looks like a sandwich with a thick "reference layer" on the bottom that is magnetized in one direction, a thin barrier layer inbetween and a thick "free layer" that stores the bit on the top. The free layer can be either magnetized in the same direction as the reference layer (0, low resistance) or in the opposite direction (1, high resistance) . The bit line is connected to the free layer, the source line is connected via a transistor to the reference layer and the word line is connected to the transistor gate. The advantages of STT-RAM are that it offers a higher density than SRAM, has a lower leakage power and is far more robust against errors so that no ECC is needed. Unfortunately, the time and energy needed to write a bit are still too high (by a factor of approx. 5 or 6 respectively). Yuan Xie and Yiran Chen explained in their talks possible hardware and cache architectures in which STT-RAM can replace or, if used in a combination, enhance traditional SRAM.

P.S.: This post is a bit delayed due to my busy traveling schedule.