Study Group: Computing models. Sublq etc.

The study group on Mar 9^th 2012 was done by Simon and Mike. The talk focused on computing models, sublq etc.

Subleq-OISC:

OISC stands for “one instruction set computer” – analogous to the well-known CISC and RISC abbreviations. The OISC instruction “set” indeed consists of only one instruction, but is nonetheless Turing-complete1. This instruction takes three parameters and is concisely described as “subtract and branch on

result less than or equal to zero,” abbreviated subleq a b c.

In “C” style pseudocode, this instruction does the following:

*b-= *a;

if (*b <= 0) goto c;

The followings are instrucions of some operations:

CLR a

subleq a a $+1

JMP c

subleq Z Z c

MOV a b

subleq b b $+1 *b=0

subleq a Z $+1 Z=-*a

subleq Z b $+1 *b=0-(-*a)=*a

subleq Z Z $+1 Z=0

ADD a b c

subleq a Z $+1

subleq b Z $+1

subleq c c $+1

subleq Z c $+1

sublez Z Z $+1

SUB a b c

subleq t t $+1

subleq s s $+1

subleq a t $+1

subleq b s $+1

subleq s t $+1

subleq c c $+1

subleq s s $+1

subleq t s $+1

subleq s c $+1

DIV abc

MOV b v

MOV a w

CLR c

subleq N c $+1

subleq w v $+4

subleq Z Z $-8

The Ultimate RISC :

The only instruction in the ultimate RISC `instruction set' is a two address instruction that moves a single word from one memory location to another. The instruction execution unit of such a machine can hardly be considered to be a processor, since it performs no computations; thus, the term central processing unit is inappropriate here. If such a machine is to be useful, it must, of course, be able to compute; this problem can be solved by adding a memory mapped arithmetic unit.

This architecture is not intended to be a practical architecture. However, the architecture can be made reasonably convenient with the addition of a small amount of extra hardware. For example, the attachment of a memory management unit between the instruction execution unit and the memory allows for indexing, and one additonal flipflop is enough to allow convenient conditional branches. Furthermore, this architecture may be pipelined, and doing this introduces all of the problems of instruction scheduling traditionally associated with RISC systems.

A minimal implementation of the ulitmate RISC architecture requires an instruction execution unit, a memory, input-output devices, and a bus to connect these. The basic algorithm executed by the instruction execution unit is most easily expressed if a memory address fits exactly in a word. This has been assumed by the register transfer description of the instruction execution unit shown as follow:

registers pc, addr, temp;

      repeat
          1: addr := M[pc]; pc := pc + 1;
          2: temp := M[addr];
          3: addr := M[pc]; pc := pc + 1;
          4: M[addr] := temp;
      forever;

The condition code tests shown in the following table are based on those available on machines descended from the PDP-11, where N signifies a negative result, Z signifies a result of zero, O signifies a 2's complement overflow, and C signifies a carry out of the sign bit. The representation of Boolean values produced by the arithmetic unit is determined by the need to perform conditional branch instructions. True is represented by the value 2, and False is represented by zero.

Table : Arithmetic Unit Operations
 


 
        
   
    
address 
   
   
    
write  
   
   
    
read
   
  
  
   
    
FFF0
   
   
    
acc = data 
data = acc
   
  
  
   
    
FFF1 
   
   
    
acc = acc-data  
   
   
    
data = N
   
  
  
   
    
FFF2
   
   
    
acc = data-acc 
   
   
    
data = Z
   
  
  
   
    
FFF3
   
   
    
acc = data+acc
   
   
    
data = O
   
  
  
   
    
FFF4
   
   
    
acc = data^acc 
   
   
    
data = C
   
  
  
   
    
FFF5
   
   
    
acc = data&acc
   
   
    
data = N^O
   
  
  
   
    
FFF6  
   
   
    
acc = data|acc 
   
   
    
data = (N^O)|Z
   
  
  
   
    
FFF7
   
   
    
acc = data>>1
   
   
    
data = C^not(Z)