Embedded Systems Week: Day 2 (Tuesday)

There were no talks directly related to the security of embedded systems on Tuesday so this entry will be about something different: "Performance Enhancement under Power Constraints using Heterogeneous CMOS-TFET Multicores" by E. Kultursay, K. Swaminathan, V. Saripalli, V. Narayanan, M. T. Kandemir and S. Datta, all from Pennsylvania State University.

Within battery powered embedded systems, you usually have strict limits on your power budget - battery development has, unfortunately, not been able to keep up with the development of computing power. Computing power has been driven mainly by three factors: Smaller transistors, higher frequencies and more cores. But it wasn't possible to scale all aspects transistors comparable to their size and frequency behaviour. Most notably, some characteristic voltage levels like the threshold voltage V_th have remained fairly constant for CMOS devices over time. This means, that the power per transistor (processor core) grows with the frequency.

To reconcile the more power-hungry multi-core devices and the limited power budget, two strategies have been developed: Dim Silicon and Dark Silicon. The Dim Silicon strategy means that many or all cores get only a small power budget allocated, forcing them to operate at low frequency in a sub-threshold setting but enabling (almost) all cores to operate simultaneously. This is great for applications which can be easily parallelized. The Dark Silicon strategy on the other hand allocates large power budgets to a few cores which can now operate at a high frequency while all the other cores are turned off completely. This is great for applications which do not profit from parallelism but work predominantly sequential. The Dark Silicon strategy is well suited for CMOS transistors (e.g. FinFET) who are fairly power efficient at high frequencies but have a fairly poor I_on/I_off characteristic in low-frequency sub-threshold settings. The Dim Silicon strategy on the other hand is fairly well suited for TFET transistors which use the quantum tunneling effect as they are fairly power efficient in low-frequency sub-threshold settings (but not at high-frequency with "full" voltage V_CC>>V_th).

This was all background to the work described in the paper. As it is fairly difficult to predict what kind of applications will be run predominantly  on a generic multi-core processor for embedded systems - you want to sell your chip to everyone, not just to some people - the authors started evaluating the possible ways to combine Dim Silicone cores implemented using TFETs and Dark Silicone cores implemented using CMOS FinFETs on the same die and, with extensive simulations, discover optimal partioning of processors, power budget and work allocation. They based their simulation on 32 Intel Atom cores of the Z5xx series and used 20nm transistor characteristics. Their first result is that the best partitioning of processors can be achieved with 24 TFET low-power cores (Dim Silicon) and 8 CMOS high-power (Dark Silicon) cores. The second result is that a dynamic allocation of power budgets and workloads resulted in the best trade-off between power consumption and performance.

You might think: "D'OH, that's sort of obvious, isn't it?" Well, no, it isn't. It does meet expectations but multi-core systems raise surprisingly complex issues and if you start mixing different transistor types for different cores, switching between different voltage and frequency levels, trade-offs don't always show the expected result. This paper has given an analysis as comprehensive as possible and will provide an important stepping stone for additional explorations. For example, one would not expect the same processor core to be used over and over again but would expect to see at least some specialized cores for multimedia applications, cryptography and communication, some of them with hard real-time constraints. These will complicate the allocation schemes further, having different power consumption characteristics.

I believe, this paper highlights some of the complexities waiting for Embedded Systems Designers (including those working on Embedded Systems security) very well and shows some very interesting directions to move forward.